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| 1 msps, 14 - bit, simultaneous sampling sar adc with pga and four comparators data sheet AD7264 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trad emarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2008 C 2012 analog devices, inc. all rights reserved. technical support www.analog.com features dual, simultaneous sampling , 14- bit, 2 - channel adc true differential analog inputs programmable gain stage: 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128 throughput rate per adc 1 msps for AD7264 500 ksps for AD7264 -5 analog inpu t impedance: >1 g wide input bandwid th ?3 db bandwidth: 1.7 mhz at gain = 2 4 on - chip comparators snr: 78 db typical at gain = 2, 71 db typical at gain = 32 device offset calibration system gain calibration on - chip reference: 2.5 v ?40c to +105c operation high speed s erial interface compatible with spi, qspi?, microwire?, and dsp 48- lead lfcsp and lqfp packages general description the AD7264 is a dual, 14 - bit, high speed, low power, successive approximation ad c that operates from a single 5 v power supply and features throughput rates of up to 1 msps per on - chip adc (500 ksps for the AD7264 -5) . two complete adc functions allow simultaneous sampling and conversion of two channels. each adc is preceded by a true differential analog input with a pga. there are 14 gain set tings available: 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, and 128. the AD7264 contain s four comparators. comparator a and comparator b are optimized for low power, whereas comparator c and comparator d have fast propagation delays. the AD7264 feature s a calibration function to remove any device offset error and programmable gain adjust registers to allow for input path (for example, sensor) offset and gain compensation. the AD7264 has an on - chip 2.5 v reference that can be disabled if an external reference is preferred . the AD7264 is available in 48 - lead lfcsp and lqfp packages. the AD7264 is ideally suited for monitoring small amplitude signals from a variety of sensors . the parts include all the functionality needed for monitoring the position feedback signals from a variety of analog encoders used in mo tor control systems. functional block dia gram agnd dgnd d out b pd1 pd0/d in pd2 v ref a av cc v a + v a ? v b + v b ? c b + c b ? c a + c a ? c d + c d ? c c + c c ? v ref b c a _c b v cc c a _c b _gnd c c _c d v cc c c _c d _gnd comp comp comp comp c out c c out b c out a c out d d out a pga t/h buf t/h buf pga 14-bit successive approximation adc ref 14-bit successive approximation adc control logic output drivers output drivers output drivers output drivers v drive g3 g2 g1 g0 cal cs sclk refsel 06732-001 AD7264 output drivers output drivers figure 1. product highlights 1. integrated pga with a variety of flexible gain settings to allow detection and co nversion of low level analog signals. 2. each pga is followed by a dual simultaneous sampling adc, featuring throughput rates of 1 msps per adc (500 ksps for the AD7264 -5) . the conversion result of both adcs is simultaneously available on separate data lines or in succession on one data line if only one serial port is available. 3. four integrated comparators that can be used to count signals from pole sensors in motor control applications. 4. internal 2.5 v reference.
important links for the AD7264 * last content update 11/13/2013 05:48 pm similar products & parametric selection tables find similar products by operating parameters high resolution - simultaneous sampling14/16/18-bit pulsar adcs documentation ms-2210: designing power supplies for high speed adc adc interfaces with multiple sensors; replaces up to three data acquisition channels in motor control applications evaluation kits & symbols & footprints view the evaluation boards and kits page for documentation and purchasing symbols and footprints design collaboration community collaborate online with the adi support team and other designers about select adi products. follow us on twitter: www.twitter.com/adi_news like us on facebook: www.facebook.com/analogdevicesinc design support submit your support request here: linear and data converters embedded processing and dsp telephone our customer interaction centers toll free: americas: 1-800-262-5643 europe: 00800-266-822-82 china: 4006-100-006 india: 1800-419-0108 russia: 8-800-555-45-90 quality and reliability lead(pb)-free data sample & buy AD7264 view price & packaging request evaluation board request samples check inventory & purchase find local distributors * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page (labeled 'important links') does not constitute a change to the revision number of the product data sheet. this content may be frequently modified. powered by tcpdf (www.tcpdf.org) AD7264 data sheet rev. b | page 2 of 28 table of contents features .............................................................................................. 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 6 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configurations and function descriptions ........................... 8 typical performance characteristics ........................................... 10 terminology .................................................................................... 14 theory of operation ...................................................................... 15 circuit information .................................................................... 15 comparators ................................................................................ 15 operation ..................................................................................... 15 analog inputs .............................................................................. 15 v drive ............................................................................................ 16 reference ..................................................................................... 16 typical connection diagrams .................................................. 17 application details ..................................................................... 19 modes of operation ....................................................................... 20 pin driven mode ........................................................................ 20 gain selection ............................................................................. 20 power - down modes .................................................................. 20 control register ......................................................................... 21 on- chip registers ...................................................................... 22 serial interface ................................................................................ 23 calibration ....................................................................................... 25 internal offset calibration ........................................................ 25 adjusting the offset calibration register ............................... 26 system gain calibration ............................................................ 26 application hints ........................................................................... 27 grounding and layout .............................................................. 27 pcb design guidelines for lfcsp .......................................... 27 outline d imensions ....................................................................... 28 ordering guide .......................................................................... 28 revision history 11/ 12 rev. a to rev. b ch anges to digital input voltage to dgnd parameter, table 3 ...... 7 updated outline dimension s ................................................................ . 28 7/08 rev. 0 to rev. a added AD7264 -5 ................................................................ universal added lqfp package ......................................................... universal changes to figure 1 .......................................................................... 1 changes to common - mode voltage range , v cm parameter ..... 3 changes to table 3 ............................................................................ 7 changes to pin configuration and function description section .......................................................................... 8 changes to f igure 29 ...................................................................... 19 updated outline dimensions ....................................................... 28 changes to ordering guide .......................................................... 29 5/08 revision 0: initial version data sheet AD7264 rev. b | page 3 of 28 specifications av cc = 4.75 v to 5.25 v, c a _c b v cc = c c _c d v cc = 2.7 v to 5.25 v, v drive = 2.7 v to 5.25 v, f s = 1 msps and f sclk = 34 mhz for the AD7264, f s = 500 ksps and f sclk = 20 mhz for the AD7264 - 5, v ref = 2.5 v internal/external; t a = ?40c to +105c, unless otherwise noted. table 1 . parameter min typ max unit test conditions/comments dynamic performance 1 f in = 100 khz sine wave signal -to - noise ratio (snr) 2 76 78 db pga gain setting = 2 signal -to - (noise + distortion) ratio (sinad) 2 74 77 db total harmonic distortion (thd) 2 ?85 ?77 db spurious - free dynamic range (sfdr) ?97 db common - mode rejection ratio (cmrr) ?76 db for pga gain setting = 2, ripple frequency of 50 hz/60 hz; see figure 17 and figure 18 adc -to - adc isolation 2 ?90 db bandwidth 3 1.2 mhz @ ?3 db; pga gain setting = 128 1.7 mhz @ ?3 db; pga gain setting = 2 dc accuracy resolution 14 bits integral nonlinearity 2 1.5 3 lsb differential nonlinearity 2 0.5 0.99 lsb guaranteed no missed codes t o 14 bits positive full - scale error 2 0.122 0.305 % fsr precalibration 0.018 % fsr postcalibration positive full - scale error match 2 0.061 % fsr zero code error 2 0.092 0.244 % fsr precalibration 0.012 % fsr postcalibration zero code error match 2 0.061 % fsr negative full - scale error 2 0.122 0.305 % fsr precalibra tion 0.018 % fsr postcalibration negative full - scale error match 2 0.061 % fsr zero code error drift 2.5 v/c analog input input voltage range, v in + and v in ? gain 2 v v ref cm v v cm = av cc /2; pga gain setting 2 common - mode voltage range , v cm v cm ? 100 mv v cm + 100 mv v v cm = 2 v; pga gain setting = 1; see figure 19 4 (v cc /2) ? 0.4 (v cc /2) + 0.2 v v cm = av cc /2; pga gain setting = 2 (v cc /2) ? 0.4 (v cc /2) + 0.4 v v c m = av cc /2; 3 pga gain setting 32 (v cc /2) ? 0.6 (v cc /2) + 0.8 v v cm = av cc /2; pga gain setting 48 dc leakage current 0.001 1 a input capacitance 3 5 pf input impedance 3 1 g reference input/output reference output voltage 5 2.495 2.5 2.505 v 2.5 v 5 mv max @ 25c reference input voltage 2.5 v dc leakage current 0.3 1 a external reference applied to pin v ref a/pin v ref b input capacitance 3 20 pf v ref a, v ref b output impedance 3 4 reference temperature coefficient 20 ppm/c v ref noise 3 20 v rms AD7264 data sheet rev. b | page 4 of 28 parameter min typ max unit test conditions/comments logic inputs input high voltage, v inh 0.7 v drive v input low voltage, v inl 0.8 v input current, i in 1 a v in = 0 v or v drive input capacitance, c in 3 4 pf logic outputs output high voltage, v oh v drive ? 0.2 v output low voltage, v ol 0.4 v floating state leakage current 1 a floating state output capacitance 3 5 pf output coding twos complement conversion rate conversion time 19 t sclk ns track - and - hold acquisition time 2 400 ns throughput rate 1 msps AD7264 500 k sps AD7264 - 5 comparators input offset comparator a and comparator b 2 4 mv t a = 25c to 105c only comparator c and comparator d 2 4 mv offset voltage drift 0 .5 v/ c all comparators input common - mode range 3 0 to 4 v c a _c b v cc = 5 v 0 to 1.7 v c a _c b v cc = 2.7 v input capacitance 3 4 pf input impedance 3 1 g i dd normal mode (static) 6 25 pf load, c out x = 0 v , v cm = av cc /2, v overdrive = 200 mv differential comparator a and comparator b 3 a c a _c b v cc = 3.3 v 6 8.5 a c a _c b v cc = 5.25 v comparator c and comparator d 60 a c c _c d v cc = 3.3 v 12 0 170 a c c _c d v cc = 5.25 v propagation delay time 2 v cm = av cc /2, v overdrive = 200 mv differential high to low, t phl comparator a and comparator b 1.4 3.5 s c a _c b v cc = 2.7 v 0.95 s c a _c b v cc = 5 v compara tor c and comparator d 0.20 0.32 s c c _c d v cc = 2.7 v 0.13 s c c _c d v cc = 5 v low to high, t plh comparator a and comparator b 2 4 s c a _c b v cc = 2.7 v 0.93 s c a _c b v cc = 5 v comparator c and comparator d 0.18 0.28 s c c _c d v cc = 2.7 v 0.1 2 s c c _c d v cc = 5 v delay matching v cm = av cc /2, v overdrive = 200 mv differential comparator a and comparator b 250 ns comparator c and comparator d 10 ns data sheet AD7264 rev. b | page 5 of 28 parameter min typ max unit test conditions/comments power requirements digital inputs = 0 v or v drive av cc 4.75 5.25 v c a _c b v cc , c c _c d v cc 2.7 5.25 v v drive 2.7 5.25 v i dd adc normal mode (static) 20 31.5 ma av cc = 5.25 v adc normal mode (dynamic) 23 33.3 ma f s = 1 msps, av cc = 5.25 v shutdown mode 0.5 1 a av cc = 5.25 v, adcs and comparators powered down power dissipation adc normal mode (static) 105 165 mw adc normal mode (dynamic) 120 175 mw shutdown mode 2.625 5.25 w 1 these specifications were determined without the use of the gain calibration feature. 2 see the terminology section. 3 samples are tested during initial release to ensure compliance; they are not subject to production testing. 4 for pga g ain = 1, to utili ze the full analog input ra nge (v cm v ref /2) of the AD7264 , the v cm voltage should be dropped to lie within a range from 1.9 5 v to 2.0 5 v. 5 refers to pin v ref a or pin v ref b. 6 this specification includes the i dd for both comparators. the i dd per comparator is the specified value divided by 2. AD7264 data sheet rev. b | page 6 of 28 timing specification s av cc = 4.75 v to 5.25 v, c a _c b v cc = c c _c d v cc = 2.7 v to 5.25 v, v ref = 2.5 v internal/external; t a = t min to t max , unless otherwise noted . 1 table 2 . limit at t min , t max parameter 2.7 v v drive 3.6 v 4.75 v v drive 5.25 v unit description f sclk 200 200 khz min 34 34 2 mhz max AD7264 20 20 mhz max AD7264 -5 t convert 19 t sclk 19 t sclk ns max t sclk = 1/f sclk 560 560 ns max AD7264 950 950 ns max AD7264 -5 t quiet 13 13 ns min minimum time between end of serial read/bus relinquish and next falling edge of cs t 2 10 10 ns min cs to sclk setup time t 3 3 15 15 ns max delay from 19 th sclk falling edge until d out a and d out b are three - state disabled t 4 29 23 ns max data access time after sclk falling edge t 5 15 13 ns min sclk to data valid hold time t 6 0.4 t sclk 0.4 t sclk ns min sclk high pulse width t 7 0.4 t sclk 0.4 t sclk ns min sclk low pulse width t 8 13 13 ns min cs rising edge to falling edge pulse width t 9 13 13 ns max cs ris ing edge to d out a, d out b high impedance/bus relinquish t 10 5 5 ns min sclk falling edge to d out a, d out b high impedance 35 35 ns max sclk falling edge to d out a, d out b high impedance t 11 2 2 s min minimum cal pin high time t 12 2 2 s min minimum time between the cal pin high and the cs falling edge t 13 3 3 ns min d in setup time prior to sclk falling edge t 14 3 3 ns min d in hold time after sclk falling edge t power - up 240 240 s max internal reference, with a 1 f decoupling capacitor 15 15 s max with an external reference, 10 s typical 1 sample tested during initial release to ensure compliance. all input signals are specified with t r = t f = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. all timing specifications given are with a 25 pf load capacitance. with a load capacitance greater than this value, a digital buffer or latch must be used. see the terminology section. 2 t he AD7264 is functional with a 40 mh z sclk at 25 c, but specified performance is not guaranteed with sclk fre quencies greater than 34 mhz. 3 the time required for the output to cross 0.4 v or 2.4 v. cs sclk 1 5 19 d out a three-s ta te t 4 2 3 4 20 t 5 three- sta te t 7 t 3 18 db 11 a db12 a db13 a 21 31 32 33 db1 a db0 a d out b three-s ta te three- sta te db 11 b db12 b db13 b db1 b db0 b 06732-002 t 2 t 9 t 8 t quiet t 6 figure 2 . serial interface timing diagram data sheet AD7264 rev. b | page 7 of 28 absolute maximum rat ings table 3 . parameter rating v drive to dgnd ?0.3 v to av cc v drive to agnd ?0.3 v to av cc av cc to agnd, dgnd ?0.3 v to +7 v c a _c b v cc to c a _c b _gnd ?0.3 v to +7 v c c _c d v cc to c c _c d _gnd ?0.3 v to +7 v agnd to dgnd ?0.3 v to +0.3 v c a _c b _gnd, c c _c d _gnd to dgnd ?0.3 v to +0.3 v analog input voltage to agnd ?0.3 v to av cc + 0.3 v digital input voltage to dgnd ?0.3 v to v drive + 0.3 v digital output voltage to gnd ?0.3 v to v drive + 0.3 v v ref a, v ref b input to agnd ?0.3 v to av cc + 0.3 v c out a, c out b, c out c, c out d to gnd ?0.3 v to v drive + 0.3 v c a , c b , c c , c d to c a _c b _gnd, c c _c d _gnd ?0.3 v to c a _c b v cc /c c _c d v cc + 0.3 v operating temperature range ?40c to +105c storage temperature range ?65c to +150c junction temperature 150c lqfp package ja thermal impedance 55 c/w jc thermal impedance 16 c/w lfcsp package ja thermal impedance 30 c/w jc thermal impedance 3 c/w pb - free temperature, soldering reflow 255c esd 2 kv stresses above those listed under absolute maximum ratings may cause perm anent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditi ons for extended periods may affect device reliability. esd caution AD7264 data sheet rev. b | page 8 of 28 pin configuration s and function descrip tions 06732-003 pin 1 indicator AD7264 top view (not to scale) 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 17 18 19 20 21 22 23 24 25 c out d 26 c out c 27 v drive 28 dgnd 29 c out b 30 c out a 31 d out b 32 d out a 33 av cc 34 sclk 35 cs 36 cal 37 g3 38 g2 39 g1 40 g0 41 av cc 42 agnd 4344 45 c b ? 46 c b + 47 c a ? 48 c a + 14 c a _c b v cc av cc v a ? v a + agnd av cc agnd v b + v b ? av cc c c _c d v cc agnd c c + c c ? c d + c d ? c c _c d _gnd v ref b agnd av cc pd2 pd1 pd0/d in refsel c a _c b _gnd v ref a figure 3 . 48 - lead lqfp pin configuration 06732-004 AD7264 top view (not to scale) c out d c out c v drive dgnd c out b c out a d out b d out a av cc sclk cal cs 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 35 36 34 33 32 31 30 29 28 27 26 25 pin 1 indicator c a _c b v cc av cc v a ? v a + agnd av cc agnd v b + v b ? av cc c c _c d v cc agnd g3 g2 g1 g0 av cc agnd c b ? c b + c a ? c a + c a _c b _gnd v ref a c c + c c ? c d + c d ? c c _c d _gnd v ref b agnd av cc pd2 pd1 pd0/d in refsel notes 1. the exposed metal paddle on the bottom of the lfcsp package must be soldered to pcb ground for proper heat dissipation and also for noise and mechanical strength benefits. figure 4 . 48 - lead lfcsp pin config uration table 4 . pin function descriptions pin no. mnemonic description 2, 7, 11, 20, 33, 41 av cc analog supply voltage, 4.75 v to 5.25 v. this is the supply voltage for the analog circuitry on the AD7264. all av cc pins can be t ied together. this supply should be decoupled to agnd with a 100 nf ceramic capacitor per supply and a 10 f tantalum capacitor. 1 c a _c b v cc comparator supply voltage, 2.7 v to 5.25 v. this is the supply voltage for comparator a and comparator b. this supply should be decoupled to c a _c b _gnd. av cc , c c _c d v cc , and c a _c b v cc can be tied together. 12 c c _c d v cc compa rator supply voltage, 2.7 v to 5.25 v. this is the supply voltage for comparator c and comparator d. this supply should be decoupled to c c _c d _gnd. av cc , c c _c d v cc , and c a _c b v cc can be tied together. 4, 3 v a +, v a ? analog inputs of adc a. true differential input pair. 9, 10 v b +, v b ? analog inputs of adc b. true differential input pair. 43, 18 v ref a, v ref b reference input/output. decoupling capacitors are connected to these pins to decouple the internal reference buffer for each respective adc. typically, 1 f capacitors are required to decouple the reference. provided the output is buffered, the on - chip reference can be taken from these pins and applied externally to the rest of a system. 34 sclk serial clock. logic input. a serial clock input provides the sclk for accessing the data from the AD7264. this clock is also used as the clock source for the conversion process. a minimum of 33 clocks are required to perform the conversion and access the 14 - bit result. 35 cs chip select. active low logic input. this input initiates conversions on the AD7264. 36 cal logic input. initiates an internal offset calibration. 21 pd2 logic input. places the AD7264 in the selected shutdown mode in conjunction with the pd1 and pd0 pins. see table 7 . 22 pd1 logic input. places the AD7264 in the selected shutdown mode in conjunction with the pd2 and pd0 pins. see table 7 . 23 pd0/d in logic input/data in put . places the AD7264 in the selected shutdown mod e in conjunction with the pd2 and pd1 pins. see table 7 . if all gain selection pins, g0 to g3, are tied low, this pin acts as the data input pin and all programming is via the control register (see table 8 ). data to be written to the AD7264 control register is provided on this input and is clocked into the register on the falling edge of sclk. data sheet AD7264 rev. b | page 9 of 28 pin no. mnemonic description 48, 47, 46, 45 c a +, c a ?, c b +, c b ? comparator inputs. these pins are the inverting and noninverting analog input s for comparator a and comparator b. these two comparators have very low power consumption. 13, 14, 15, 16 c c +, c c ?, c d +, c d ? comparator inputs. these pins are the inverting and noninverting analog inputs for comparator c and comparator d. these two com parators offer very fast propagation delays. 5, 6, 8, 19, 42 agnd analog ground. ground reference point for all analog circuitry on the AD7264. all analog input signals and any external reference signal should be referred to this agnd voltage. all agnd p ins should be connected to the agnd plane of a system. the agnd, dgnd, c a _c b _gnd, and c c _c d _gnd voltages should ideally be at the same potential and must not be more than 0.3 v apart, even on a transient basis. c a _c b _gnd and c c _c d _gnd can be tied to agnd. 28 dgnd digital ground. ground reference point for all digital circuitry on the AD7264. the dgnd pin should be connected to the dgnd plane of a system. the dgnd and agnd voltages should ideally be at the same potential and must not be more than 0.3 v apa rt, even on a transient basis. 30, 29, 26, 25 c out a, c out b, c out c, c out d comparator outputs. these pins provide a cmos (push - pull) output from each respective comparator. these are digital output pins with logic levels determined by the v drive supply. 3 2, 31 d out a, d out b serial data outputs. the data output from the AD7264 is supplied to each pin as a serial data stream in twos complement format. the bits are clocked out on the falling edge of the sclk input. a total of 33 sclk cycles are required to perform the conversion and access the 14 - bit data. during the conversion process, the data output pins are in three - state and, when the conversion is completed, the 19 th sclk edge clocks out the msb. the data appears simultaneously on both pins from the simul taneous conversions of both adcs. the data is provided msb first. if cs is held low for a further 14 sclk cycles on either d out a or d out b following the initial 33 sclk cycles, the data from the other adc follows on the d out pin. this allo ws data from a simultaneous conversion on both adcs to be gathered in serial format on either d out a or d out b using only one serial port. 40, 39, 38, 37 g0, g1, g2, g3 logic inputs. these pins are used to program the gain setting of the front - end amplifie rs. if all four pins are tied low, the pd0/d in pin acts as a data input pin, d in , and all programming is made via the control register. see table 6 . 27 v drive logic power supply input, 2.7 v to 5.25 v. the voltage supplied at this pin determines at what voltage the interface operates, including the comparator outputs. this pin should be decoupled to dgnd. 44, 17 c a _c b _gnd, c c _c d _gnd comparator ground. ground reference point for all comparator circuitry on the AD7264. both th e c a _c b _gnd and c c _c d _gnd pins should connect to the gnd plane of a system and can be tied to agnd. the dgnd, agnd, c a _c b _gnd, and c c _c d _gnd voltages should ideally be at the same potential and must not be more than 0.3 v apart, even on a transient basis. 24 refsel internal/external reference selection. logic input. if this pin is tied to a logic high voltage, the on - chip 2.5 v reference is used as the reference source for both adc a and adc b. if the refsel pin is tied to gnd, an external reference can be supplied to the AD7264 through the v ref a and/or v ref b pins. AD7264 data sheet rev. b | page 10 of 28 typical performance characteristics ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 av cc = 5v v drive = 5v f s = 1msps t a = 25c internal reference gain = 2 06732-005 code dnl error (lsb) figure 5 . typical dnl at gain of 2 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 av cc = 5v v drive = 5v f s = 1msps t a = 25c internal reference gain = 2 06732-006 code inl error (lsb) figure 6 . typical inl at gain of 2 06732-009 frequency (khz) (db) ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 av cc = 5v v drive = 2.7v f s = 1msps t a = 25c f in = 100khz internal reference snr = 79db thd = ?96db gain = 2 0 50 100 150 200 250 300 350 400 450 figure 7 . typical fft at gain of 2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 av cc = 5v v drive = 5v f s = 1msps t a = 25c internal reference gain = 32 06732-007 code dnl error (lsb) figure 8 . typical dnl at gain of 32 ?2.0 ?1.5 ?1.5 ?1.0 ?1.0 ?0.5 ?0.5 0 2.0 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 av cc = 5v v drive = 5v f s = 1msps t a = 25c internal reference gain = 32 06732-008 code inl error (lsb) figure 9 . typical inl at gain of 32 06732-010 frequency (khz) (db) ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 50 100 150 200 250 300 350 400 450 500 av cc = 5v v drive = 2.7v f s = 1msps t a = 25c f in = 100khz internal reference snr = 72db thd = ?87db gain = 32 figure 10 . typical fft at gain of 32 data sheet AD7264 rev. b | page 11 of 28 06732-011 code number of hits 0 1000 2000 3000 4000 5000 6000 7000 8000 8189 8190 8191 8192 8193 8194 1117 6 0 7793 1084 0 figure 11 . histogram of codes for 10k samples at gain of 2 06732-012 code number of hits 0 500 1000 1500 2000 2500 3000 8186 8187 8188 8189 8190 8191 8192 8193 8194 8195 8196 8197 2486 2180 1222 498 132 22 2 1081 381 82 16 1861 figure 12 . histogram of codes for 10k samples at gain of 32 06732-014 analog input frequency (khz) thd (db) ?90 ?85 ?80 ?75 ?70 ?65 10 110 210 310 410 510 610 710 810 910 av cc = 5v v drive = 5v f s = 1msps internal reference gain = 2 gain = 32 figure 13 . thd vs. analog input frequency up to 1 mhz at gain of 2 and 32 2.4961 2.4962 2.4963 2.4964 2.4965 2.4966 2.4967 2.4968 0 20 40 60 80 100 120 140 160 180 200 av cc = 5v v drive = 3v f s = 1msps internal reference 06732-015 current load ( a) v ref (v) figure 14 . v ref vs. reference output current drive 600 1900 1800 06732-016 gain 3db bandwidth (khz) 1 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 2 3 4 6 8 12 16 24 32 48 64 96 128 av cc = 5v v drive = 5v f s = 1msps internal reference figure 15 . 3 db bandwidth vs. gain 30 35 40 45 50 55 60 65 70 75 80 1 2 3 4 6 8 12 16 24 32 48 64 96 128 06732-017 pga gain snr (db) av cc = 5v v drive = 5v f s = 1msps internal reference f in = 100khz figure 16 . snr vs. pga gain for an analog input tone of 100 khz AD7264 data sheet rev. b | page 12 of 28 ?90 ?88 ?86 ?84 ?82 ?78 ?76 ?74 ?72 ?80 ?70 1 2 3 4 6 8 12 16 24 32 48 64 96 128 06732-018 gain cmr (db) av cc = 5v v drive = 5v f s = 1msps internal reference f ripple = 50khz figure 17 . common - mode rejection vs. gain ?80 ?79 ?78 ?77 ?76 ?75 ?74 ?73 ?72 ?71 ?70 0 20 40 60 80 100 120 140 160 180 200 06732-019 ripple frequency (khz) cmr (db) av cc = 5v v drive = 5v f s = 1msps v ripple = 700mv p-p gain = 2 internal reference figure 18 . common - mode rejection vs. common - mode ripple frequency ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 g = 2 g = 3 g = 12 g = 24 g 32 g = 8 g = 16 06732-020 v cm range (v) thd (db) av cc = 5v v drive = 5v f s = 1msps f in = 100khz internal reference g = 1 g = 4 g = 6 figure 19 . thd vs. common - mode voltage range for various pga gain settings 06732-021 overdrive voltage (mv) propagation delay ( s) 0 1 2 3 4 5 6 7 8 9 10 0 10 20 30 40 50 60 70 80 90 100 l to h, c a _c b v cc = 4.5v l to h, c a _c b v cc = 5v h to l, c a _c b v cc = 3.6v h to l, c a _c b v cc = 4.5v h to l, c a _c b v cc = 5v h to l, c a _c b v cc = 2.7v l to h, c a _c b v cc = 3.6v l to h, c a _c b v cc = 2.7v av cc = 5v v drive = 3.3v t a = 25c figure 20 . propagation delay for comparator a and comparator b vs. overdrive voltage for various supply voltages 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 06732-022 overdrive voltage (mv) propagation delay ( s) 0 10 20 30 40 50 60 70 80 90 100 h to l, c c _c d v cc = 4.5v h to l, c c _c d v cc = 5v l to h, c c _c d v cc = 3.6v l to h, c c _c d v cc = 4.5v l to h, c c _c d v cc = 5v l to h, c c _c d v cc = 2.7v h to l, c c _c d v cc = 3.6v h to l, c c _c d v cc = 2.7v av cc = 5v v drive = 3.3v t a = 25c figure 21 . propagation delay for comparator c and comparator d vs. overdrive voltage for various supply voltages 06732-036 supply ripple frequency (khz) psrr (db) ?120 ?115 ?110 ?105 ?100 ?95 ?90 ?85 ?80 ?75 0 200 400 600 800 1000 ?70 v drive = 5v gain = 2 t a = 25c internal reference 100mv p-p sine wave on av cc av cc decoupled with 10f and 100nf capacitors figure 22 . power supply rejection ratio data sheet AD7264 rev. b | page 13 of 28 ?300 ?200 ?100 0 100 200 300 06732-037 current (ma) v out (v) or v dd ? v out (mv) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 c out a/c out b source current c out c/c out d source current c out a/c out b sink current c out c/c out d sink current d out sink current d out source current figure 23 . d out and c out source and sink current AD7264 data sheet rev. b | page 14 of 28 terminology differential nonlinearity (dnl) differential nonlinearity is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. integral nonlinearity (inl) integral nonlinearity is the maximum deviation from a straight line passing through the endpoints of the adc transfer fun ction. the endpoints of the transfer function are zero scale, a single (1) lsb point below the first code transition, and full scale , a point 1 lsb above the last code transition. zero code error this is the deviation of the midscale transition (all 1s to all 0s) from the ideal v in voltage, that is, v cm ? ? lsb. positive full - scale error this is the deviation of the last code transition (011 110 to 011 111) from the ideal, that is, lsb1 2 ? ? ? ? ? ? ? + gain v v ref cm after the zero code error has been adjusted out. negative full - scale error this is the deviati on of the first code transition (10 000 to 10 001) from the ideal, that is, lsb1 2 + ? ? ? ? ? ? ? gain v v ref cm after the zero code error has been adjusted out. zero code error match this is the difference in zero code error across both adcs. positive full - scal e error match this is the difference in positive full - scale error across both adcs. negative full - scale error match this is the difference in negative full - scale error across both adcs. track - and - hold acquisition time the track - and - hold amplifier returns t o track mode at the end of conversion. track - and - hold acquisition time is the time required for the output of the track - and - hold amplifier to reach its final value, within 1/2 lsb, after the end of conversion. signal -to - (noise + distortion) ratio this ratio is the measured ratio of signal - to - (noise + distortion) at the output of the analog - to - digital converter. the signal is the rms amplitude of the fundamental. noise is the sum of all non - fundamental signals up to half the sampling frequency (f s /2), exclu ding dc. the ratio is dependent on the number of quan - tization levels in the digitization process; the more levels, the smaller the quantization noise. the theoretical signal -to - (noise + distortion) ratio for an ideal n- bit converter with a sine wave inpu t is given by signal - to -( noise + distortion ) = (6.02 n + 1.76) db thus , for a 14 - bit converter, this is 86 db. total harmonic distortion (thd) total harmonic distortion is the ratio of the rms sum of harmonics to the fundamental. for the AD7264, it is defin ed as 1 6 54 32 v vvvvv thd 22222 log20 (db) ++++ = where v 1 is the rms amplitude of the fundamenta l and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic, or spurious noise, is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2, excluding dc) to the rms value of the fun - damental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs w here the harmonics are buried in the noise floor, it is a noise peak. adc -to - adc isolation adc - to - adc isolation is a measure of the level of crosstalk between adc a and adc b. it is measured by applying a full - scale, 100 khz sine wave signal to all unsele cted input channels and determining how much that signal is attenuated in the selected channel with a 40 khz signal. the figure given is the worst - case. power supply rejection ration (psrr) variations in power supply affect the full - scale transition but n ot the linearity of the converter. psrr is the maximum change in the full - scale transition point due to a change in power supply voltage from the nominal value (see figure 22). propagation delay time, low to high (t plh ) propagatio n delay time from low to high is defined as the time taken from the 50% point on a low to high input signal until the digital output signal reaches 50% of its final low value. propagation delay time, high to low (t phl ) propagation delay time from high to low is defined as the time taken from the 50% point on a high to low input signal until the digital output signal reaches 50% of its final high value. comparator offset comparator offset is the measure of the density of digital 1s and 0s in the comparator output when the negative analog terminal of the comparator input is held at a static potential, and the analog input to the positive terminal of the comparators is varied proportionally about the static negative terminal voltage . data sheet AD7264 rev. b | page 15 of 28 theory of operation ci rcuit information the AD7264 is a fast, dual, simultaneous sampling, differential, 14- bit, serial adcs . the AD7264 contain s two on - chip diffe - rential programmable gain amplifiers, two track - and - hold amplifiers, and two successive approximation analog - to - di gital converters with a serial interface with two separate data output pins. the AD7264 also include s four on - chip comparators. the part is housed in a 48 - lead lfcsp or 48 -lead lqfp package, offering the user considerable space - saving advantages over alter native solutions. the AD7264 require s a low voltage 5 v 5% av cc to power the adc core and supply the digital power, a 2.7 v to 5.25 v c a _c b v cc , c c _c d v cc supply for the comparators , and a 2.7 v to 5.25 v v drive supply for interface power. the on - board pga allows the user to select from 14 program - mable gain stages: 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, and 128. the pga accepts fully differential analog signals. the gain can be selected either by setting the logic state of the g0 to g3 pins or by programming the control register. the serial clock input accesses data from the part while also providing the clock source for each successive approximation adc. the AD7264 ha s an on - chip 2.5 v reference that can be disabled when an external r eference is preferred. if the internal reference is used elsewhere in a system, the output from v ref a and v ref b must first be buffered. if the internal reference is the preferred option, the user must tie the refsel pin to a logic high voltage. alternative ly, if refsel is tied to gnd, an external reference can be supplied to both adcs through the v ref a and v ref b pins (see the reference section). the AD7264 also feature s a range of power - down options to allow the user great flexibility with the independent circuit components while allowing for power savings between conver - sions. the power - down feature is implemented via the control register or the pd0 to pd2 pins, as described in the control register section . comparators the AD7264 ha s four on - chip comparators. comparator a and comparator b hav e ultralow power consumption , with static power consumption typically less than 10 w with a 3.3 v supply. comparator c and comparator d feature very fast propagation d elays of 130 ns for a 200 mv differential overdrive. these comparators have push - pull output stages that operate from the v drive supply. this feature allows operation with a minimum amount of power consumption. each pair of comparators operates from it s own independent supply, c a _c b v cc or c c _c d v cc . the comparators are specified for supply voltages from 2.7 v to 5.25 v. if desired, c a _c b v cc and c c _c d v cc can be tied to the av cc supply. the four compa - rators on the AD7264 are functional with c a _c b v cc , c c _c d v cc greater than or equal to 1.8 v. however, no specifica tions are guaranteed for comparator supplies less than 2.7 v. the wide range of supply voltages ensures that the comparators can be used in a variety of battery backup modes. the four on - chip comp arators on the AD7264 are ideally suited for monitoring signals from pole sensors in motor control systems. the comparators can be used to monitor signals from hall effect sensors or the inner tracks from an optical encoder. one of the comparators can be u sed to count the index marker or z marker, which is used on startup to place the motor in a known position. operation the AD7264 ha s two successive approximation adcs, each based around two capacitive dacs and two programmable gain amplifiers. the adc it self comprises control logic, a sar, and two capacitive dacs. the control logic and the charge redistribution dacs are used to add and subtract fixed amounts of charge from the sam - pling capacitor amplifiers to bring the comparator back into a balanced con dition. when the comparator is rebalanced, the conversion is complete. the control logic generates the adc output code. each adc is preceded by its own programmable gain stage. the pga features high analog input impedance, true differential analog inputs that allow the output from any source or sensor to be connected directly to the pga inputs without any requirement for additional external buffering. the variable gain settings ensure that the device can be used for amplifying signals from a variety of sou rces. the AD7264 offer s the flexibility to choose the most appropriate gain setting to utilize the wide dynamic range of the device. analog inputs each adc in the AD7264 has two high impedance differential analog inputs. figure 24 shows the equivalent circuit of the analog input structure of the AD7264. it consists of a fully differential input amplifier th at buffers the analog input signal and provides the gain selected by using the gain pins. the two diodes provide esd protecti on. care must be taken to e nsure that the analog input signals never exceed the supply rails by more than 300 mv. this causes these diodes to become forward - biased and to start conducting current into the substrate. these diodes can conduct up to 10 ma wit hout causing irreversible damage to the part. the c1 capacitors in figure 24 are typically 5 pf and can primarily be attributed to pin capacitance. AD7264 data sheet rev. b | page 16 of 28 06732-024 c1 v in ? v dd c1 v in + v ou t ? v out + v dd amp amp figure 24 . analog input structure the AD7264 can accep t differential analog inputs from ? ? ? ? ? ? ? gain 2 v v ref cm to ? ? ? ? ? ? + gain 2 v v ref cm . table 5 details the analog input range f or the AD7264 for the various pga gain settings. v ref = 2.5 v and v cm = 2.5 v (av cc /2, with av cc = 5 v) . table 5 . analog input range for various pga gain settings pga gain setting analog input range for v in + and v in 1 0.75 v to 3.25 v 1 2 1.875 v to 3.125 v 3 2.083 v to 2.916 v 4 2.187 v to 2.813 v 6 2.292 v to 2.708 v 8 2.344 v to 2.656 v 12 2.396 v to 2.604 v 16 2.422 v to 2.578 v 24 2.448 v to 2.552 v 32 2.461 v to 2.539 v 48 2.474 v to 2.526 v 64 2.48 0 v to 2.520 v 96 2.487 v to 2.513 v 128 2.490 v to 2.510 v 1 for v cm = 2 v. if v cm = av cc /2, the analog input range for v in + and v in ? is 1.6 v to 3.4 v. when a full - scale step input is applied to either differential input on the AD7264 while the other analog input is held at a constant voltage, 3 s of settling time is typically required prior to capturing a stable digital output code. transfer function the AD7264 output is twos complement; the ideal transfer function is shown in figure 25. the designed code transitions occur at successive integer lsb values (that is, 1 lsb, 2 lsb , and so on). the lsb size is dependent on the analog input range selected. the lsb size for the AD7264 is ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + 384,16 2 2 2 gain v v gain v v ref cm ref cm 06732-025 100...000 01 1... 11 1 adc code 0v 100...001 100...010 01 1... 1 10 000...001 11 1... 11 1 000...000 analog input notes 1. full-scale range (fsr) = v in + ? v in ?. (v cm + (fsr/2)) ? 1lsb (v cm ? (fsr/2)) + 1lsb figure 25 . twos complement transfer function v drive the AD7264 ha s a v drive feature to control the voltage at which the serial interface operates. v drive allows the adc and the comparators to easily interface to both 3 v and 5 v processors. f or example, when the AD7264 is operated with av cc = 5 v, t h e v drive pin can be powered from a 3 v supply, allowing a large analog input range with low voltage digital processors. reference the AD7264 can operate with either the internal 2.5 v on - chip refe rence or an externally applied reference. the logic state of the refsel pin determines whether the internal reference is used. the internal reference is selected for both adcs when the refsel pin is tied to logic high. if the refsel pin is tied to agnd, an external reference can be supplied through the v ref a and/or v ref b pins. on power - up, the refsel pin must be tied to either a low or high logic state for the part to operate. suitable reference sources for the AD7264 include the ad780 , ad1582 , adr431 , ref193 , and adr391 . the internal referenc e circuitry consists of a 2.5 v band gap refer - ence and a reference buffer. when operating the AD7264 in internal reference mode, the 2.5 v internal reference is available at the v ref a and v ref b pins, which should be decoupled to agnd using a 1 f capacito r. it is recommended that the internal refer - ence be buffered before applying it elsewhere in the system. the internal reference is capable of sourcing up to 90 a of current when the converter is static. if internal reference operation is required for the adc conversion, the refsel pin must be tied to logic high on power - up. the reference buffer requires 240 s to power up and charge the 1 f decoupling capacitor during the power - up time. data sheet AD7264 rev. b | page 17 of 28 typical connection d iagrams figure 26 and figure 27 are typical connection diagrams for the AD7264. in these configurations, the agnd pin is connected to the analog ground plane of the system, and the dgnd pin is connected to the digital ground plane of the system. the a nalog inputs on the AD7264 are true differential and have an input impedance in excess of 1 g; thus, no driving op amps are required. the AD7264 can operate with either an internal or an external reference. in figure 26 , the AD7264 is configured to operate in control register mode; thus, g0 to g3, pd1, and pd2 can be co nnected to ground (low logic state). figure 27 has the gain pins configured for a gain of 2 setup; thus, the device is in pin driven mode. both circuit configurations illustrate the use of the internal 2.5 v reference. the c a _c b v cc and c c _c d v cc pins can be connected to either a 3 v or 5 v supply voltage. the av cc pin must be connected to a 5 v supply. all supplies should be decoupled with a 100 nf capacitor at the device pin , and some supply sources may require a 10 f capacitor where the source is supplied to the circuit board. the v drive pin is connected to the supply voltage of the microprocessor. the voltage applied to the v drive input controls the voltage of the serial in terface. v drive can be set to 3 v or 5 v. 10f 1 100nf v drive v drive 3v or 5v supply microprocessor/ microcontroller 10f 1 comparator supply 3v to 5v 2 100nf 100nf 100nf analog supply +5v 10 f 1 1 00nf 1 00nf 1 00nf 1 00nf 1 00nf c c+ c c? c d+ c d? c b? c b+ c a? c a+ c out d c out c c out b c out a v drive g0 g1 g2 g3 sclk d out a d out b refsel cal pd0/d in pd1 pd2 13 14 15 16 45 46 47 48 25 26 29 30 22 23 06732-026 36 24 32 35 34 37 38 39 40 27 31 21 3.125v v a? and v a+ connect directly to sensor outputs this reference signal must be buffered before it can be used elsewhere in the circuit 2.500v 1.875v gain 2 3.125v 2.500v 1.875v gain 2 3.125v 2.500v 1.875v gain 2 3.125v 2.500v 1.875v gain 2 v b? and v b+ connect directly to sensor outputs 1f 1f c c? c d? gnd c a? c b? gnd c c? c d v cc c a? c b v cc agnd agnd agnd agnd agnd dgnd av cc av cc av cc av cc av cc av cc 17 44 5 6 8 19 42 28 2 7 11 20 41 12 1 33 v b? v b+ v ref b v ref a v a+ v a? 10 9 18 43 4 3 AD7264 f ast pro p ag a tion del ay com p ar at or inputs 1 these ca p aci t ors are placed a t the supp ly source and m ay not be required in al l systems. 2 this supp ly can be connected t o the analog 5v supp ly if required. low power com p ar at or inputs serial interface cs figure 26 . typical connection diagram for the AD7264 in control register mode (all gain pins tied to ground) configured for a pga gain of 2 AD7264 data sheet rev. b | page 18 of 28 10f 1 100nf v drive v drive v drive 3v or 5v supply microprocessor/ microcontroller 10f 1 comparator supply 3v to 5v 2 both comparators and adcs powered on 100nf 100nf 100nf analog supply +5v 10 f 1 1 00nf 1 00nf 1 00nf 1 00nf 1 00nf c c+ c c? c d+ c d? c b? c b+ c a? c a+ c out d c out c c out b c out a v drive g0 g1 g2 g3 sclk d out a d out b refsel cal pd0/d in pd1 pd2 13 14 15 16 45 46 47 48 25 26 29 30 22 23 06732-027 36 24 32 35 34 37 38 39 40 27 31 21 1f 1f c c? c d? gnd c a? c b? gnd c c? c d v cc c a? c b v cc agnd agnd agnd agnd agnd dgnd av cc av cc av cc av cc av cc av cc 17 44 5 6 8 19 42 28 2 7 11 20 41 12 1 33 v b? v b+ v ref b v ref a v a+ v a? 10 9 18 43 4 3 AD7264 v drive v drive f ast pro p ag a tion del ay com p ar at or inputs 1 these ca p aci t ors are placed a t the supp ly source and m ay not be required in al l systems. 2 this supp ly can be connected t o the analog 5v supp ly if required. low power com p ar at or inputs serial interface gain 2 setup v a? and v a+ connect directly to sensor outputs this reference signal must be buffered before it can be used elsewhere in the circuit gain 2 gain 2 gain 2 gain 2 v b? and v b+ connect directly to sensor outputs cs 3.125v 2.500v 1.875v 3.125v 2.500v 1.875v 3.125v 2.500v 1.875v 3.125v 2.500v 1.875v figure 27 . typical connection diagram for the AD7264 in pin driven mode with gain of 2 and both adcs and comparators fully powered on comparator application details the comparators on the AD7264 have been designed with no internal hysteresis, allowing users the flexibilit y to add external hysteretic if required for sys tems operating in noisy environ ments . if the comparators on the AD7264 are used with external hyste - resis, some external resistors and capacitors are required, as shown in figure 28. the value of r f and r s , the external resistors , can be determined using the following equation, depending on the amount of hysteresis required in the application: cc x f s s hs vcc rr r v _ x + = where c x _c x v cc = c a _c b v cc or c c _c d v cc . the amount of hysteresis chosen must be sufficient to eliminate the effects of analog noise at the comparator inputs, which may affect the stability of the comparator outputs. the level of hysteresis required in any system depends on the noise in the system; thus, the value of r f and r s needs to be carefully selected to eliminate any noise effects . to increase the level of hysteresis in the system, increase the value of r s or r f . for example, r f = 10 m, r s = 1 k gives 330 v of hysteresis with a c x _c x v cc of 3.3 v; if hysteresis is increased to 1 mv, r s = 3.1 k. in certain applications , a load capacitor (100 pf) may be required on the comparator outputs to suppress high frequency transient glit ches. data sheet AD7264 rev. b | page 19 of 28 06732-028 r s r f c x? c x+ r s sensor c out x figure 28 . recommended comparator connection diagram application details the AD7264 has been specifically designed to meet the require - ments of any motor control shaft position feedback loop. the device can interface direct ly to multiple sensor types, including optical encoders, magneto resistive sensors, and hall effect sensors . i ts flexible analog inputs, which incorporate programmable gain , ensure that identical board design can be utilized for a variety of sensors, which results in reduced design cycles and costs. the two simultaneous sampling adcs are used to sample the sine and cosine outputs from the sensor. no external buffering is required between the sensor/transducer and the analog inputs of the AD7264. the on - chip comparators can be used to monitor the pole sensors, which can be hall effect sensors or the inner tracks from an optical encoder. figure 29 shows how the AD7264 can be used in a typical application . an optical encoder is shown i n figure 29 , but other sensor types could as easily be used. figure 29 indicates a typical application configuration only; there are several other configurations that render equally effect ive results. v a + v a ? v b + v b ? v ref b z b a u v w comp comp h.e. c b + c b ? c a + c a ? c d + c d ? c c + c c ? c a _c b v cc c a _c b _gnd c c _c d v cc c c _c d _gnd 06732-029 agnd dgnd d out b pd1 pd0/d in pd2 v ref a av cc comp comp comp comp c out c c out b c out a c out d d out a pga t/h buf t/h buf pga 14-bit successive approximation adc ref 14-bit successive approximation adc control logic output drivers output drivers output drivers output drivers v drive g3 g2 g1 g0 cal cs sclk refsel AD7264 output drivers output drivers figure 29 . typical system connection diagram with optical encoder AD7264 data sheet rev. b | page 20 of 28 modes of operation the AD7264 allows the user to choose between two modes of operation : pin driven mode a nd control register mode. pin driven m ode p in driven mode allows the user to select the gain of the pga, the power - down mode, internal or external reference, and to initiate a calibration of the offset for both adc a and adc b. these functions are implemented by setting the logic levels on the gain pins (g3 to g0), the power - down pins (pd2 to pd0), the refsel pin, and the cal pin, respectively. the logic state of the g3 to g0 pins determines which mode of operation is selected. pin driven mode is selected if at least one of the gain pins is se t to a logic high state. alternatively, if all four gain pins are connected to a logic low, the control register mode of operation is selected. gain selection the on - board pga allows the user to select from 14 program - mable gain stages: 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, and 128. the pga accepts fully differential analog signals and provides three key functions, which include selecting gains for small amplitude input signals, driving the adcs switched capacitive load, and buffering the source from the switching effects of the sar adcs. the AD7264 offer s the user great flexibility in user interface, offering gain selection via the control register or by driving the gain pins to the desired logic state. the AD7264 ha s four gain pins, g 3, g2, g1 and g0, as shown in figure 3 and figure 4 . each gain setting is selected by setting up the appropriate logic state on each of the four gain pins, as outlined in table 6 . if all four gain pins are connected to a logic low level, the part is put in control register mode, and the gain settings are selected via the control register. table 6 . gain selection g3 g2 g1 g0 gain 0 0 0 0 software control via control register 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 6 0 1 1 0 8 0 1 1 1 12 1 0 0 0 16 1 0 0 1 24 1 0 1 0 32 1 0 1 1 48 1 1 0 0 64 1 1 0 1 96 1 1 1 0 128 power - down modes the AD7264 offer s the user several of power - down optio ns to enable individual device components to be powered down independently. these options can be chosen to optimize power dissipation for different application requirements. the power - down modes can be selected by either programming the device via the control register or by driving the pd pins to the appropriate logic levels. by setting the pd pins to a logic low level when in pin driven mode, all four comparators and both adcs can be powered down. the pd2 and pd0 pins must be set to logic high and the pd1 pin set to logic low level to power up all circuitry on the AD7264. the pd pin configurations for the various power - down options are outlined in table 7 . table 7 . power - down modes pd2 pd1 pd0 comparator a, comparator b comparator c, comparator d adc a, adc b 0 0 0 off off off 0 0 1 off off on 0 1 0 off on off 0 1 1 on off off 1 0 0 on on off 1 0 1 on on on 1 1 1 1 1 1 off off off 1 pd2 = pd1 = pd0 = 1; resets the AD7264 when in pin driven mode only . the av cc and v drive supplies must continue to be supplied to the AD7264 when the comparators are powered up but the adcs are powered down. external diodes can be used from the c a _c b v cc and/or c c _c d v cc to both the av cc and the v drive supplies to ensure th at they retain a supply at all times. the AD7264 can be reset in pin driven mode only by setting the pd pins to a logic high state. when the device is reset, all the registers are cleared and the four comparators and the two adcs are left powered down. i n the normal mode of operation with the adcs and compara - tors powered on, the c a _c b v cc /c c _c d v cc suppl ies and the av cc supply can be at different voltage levels, as indicated in table 1 . when the comparators on the AD7264 are in po wer - down mode and the c a _c b v cc /c c _c d v cc supplies are at a potential 0.3 v greater than or less than the av cc supply, the supplies consume more current than would be the case if both sets of supplies were at the same potential. this configuration does not d amage the AD7264 but results in additional current flowing in any or all of the AD7264 supply pins. this is due to esd protec tion diodes within the device. in applications where power consumption in power - down mode is critical, it is recommended that the c a _c b v cc /c c _c d v cc supply and the av cc supply be held at the same potential. data sheet AD7264 rev. b | page 21 of 28 power - up conditions on power - up, the status of the gain pins determines which mode of operation is selected, as outlined in the gain selection section. al l registers are set to 0. if the AD7264 is powered up in pin driven mode, the gain pins and the pd pins should be configured to the appropriate logic states and a calibration initiated if required. alternatively, if the AD7264 is powered up in control re gister mode, the comparators and adcs are powered down and the default gain is 1. thus, powering up in control register mode requires a write to the device to power up the comparators and the adcs. it takes the AD7264 15 s to power up when using an external reference. when the internal reference is used, 240 s are required to power up the AD7264 with a 1 f decoupling capacitor. control register the control register on the AD7264 is a 12 - bit read and write register th at is used to control the device when not in pin driven mode. the pd0/d in pin serves as the serial d in pin for the AD7264 when the gain pins are set to 0 (that is, the part is not in pin driven mode). the control register can be used to select the gain of the pgas, the power - down modes, and the calibration of the offset for both adc a and adc b. when in the control register mode of operation, pd1 and pd2 should be connected to a low logic state. these functions can also be implemented by setting the logic levels on the gain pins, power - down pins, and cal pin, respectively. the control register can also be used to read the offset and gain registers. data is loaded from the pd0/d in pin of the AD7264 on the falling edge of sclk when cs is in a logic low state. the control register is selected by first writing the appropriate four wr bits, as outlined in table 10 . the 12 data bits must then be clocked into the control register of the device. thus, on the 16 th falling sc lk edge, the lsb is clocked into the device. one more sclk cyc le is then required to write to the internal device registers . in total, 17 sclk cycles are required to successfully write to the AD7264. the data is transferred on the pd0/d in line while the co nversion result is being processed. the data transferred on the d in line corresponds to the AD7264 configuration for the next conversion. only the information provided on the 12 falling clock edges after the cs falling edge and the initi al four write address bits is loaded to the control register. the pd0/d in pin should have a logic low state for the four bits rd3 to rd0 when using the control register to select the power - down modes and gain setting, or when initia - lizing a calibration. t he rd bits should also be set to a logic low level to access the adc results from both d out a and d out b. the power - up status of all bits is 0, and the msb denotes the first bit in the data stream. the bit functions are outlined in t able 9 . table 8 . control register bits msb lsb bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rd3 rd2 rd1 rd0 cal pd2 pd1 pd0 g3 g2 g1 g0 table 9 . control register bi t function descriptions bits mnemonic comment 11 to 8 rd3 to rd0 register address bits. these bits select which register the subsequent read is from. see table 11 . 7 cal setting this bit high initiates an internal offset calibration. when the calibration is completed, this pin can be reset low , and the internal offset that is stored in the on - chip offset registers is automatically removed from the adcs results. 6 to 4 pd2 to pd0 power - down bits. these bits select which power - do wn mode is programmed. see table 7 . 3 to 0 g3 to g0 gain selection bits. these bits select which gain setting is used on the front - end pga. see table 6 . table 10 . write address b its wr3 wr2 wr1 wr0 read register addressed 0 0 0 1 control register cs sclk d out a pd0/d in 06732-030 10 14 16 three-s ta te 11 12 13 17 three- s ta te 15 db12 db13 18 20 19 32 33 db0 three-s ta te wr1 wr0 rd3 rd2 rd1 rd0 ca l pd2 pd1 pd0 g3 g2 g1 g0 wr2 wr3 t 2 t 8 t quiet 9 8 7 65432 1 t 13 t 14 figure 30 . timing diagram for a write operation to the control register AD7264 data sheet rev. b | page 22 of 28 on- chip registers the AD7264 contains a control register, two offset registers fo r storing the offsets for each adc, and two external gain registers for stor ing the gain error. the control, offset , and gain registers are read and write registers. on power - up, all registers in the AD7264 are set to 0 by default. writing to a register d ata is loaded from the pd0/d in pin of the AD7264 on the falling edge of sclk when cs is in a logic low state. four address bits and 12 data bits must be clocked into the device. thus, on the 16 th falling sclk edge, the lsb is clocked into the AD7264. one more sclk cycle is then required to write to the internal device registers. in total, 17 sclk cycles are required to successfully write to the AD7264. the control and offset registers are 12 - bits registers, and the gain registers are 7 - bit registers. when writing to a register, the user must first write the address bits corresponding to the selected register. table 11 shows the decoding of the address bits. the four rd bits are written msb first, that is, rd3 followed by rd2, rd1, and rd0. the AD7264 decode s these bits to determine which register is being addressed. the subsequent 12 bits of data are written to the addressed register. when writing to the external gain registers, the seven bits of data immediately after the four address bits are written to the register . however, 17 sclk cycles are still required , and the pd0/d in pin of the AD7264 should be tied low for the five additional clock cycles . table 11 . read and write register add resses rd3 rd2 rd1 rd0 comment 0 0 0 0 adc result (default) 0 0 0 1 control register 0 0 1 0 offset adc a internal 0 0 1 1 offset adc b internal 0 1 0 0 gain adc a external 0 1 0 1 gain adc b external reading from a register the internal offset of the device, which has been measured by the AD7264 and stored in the on - chip registers during the calibration, can be read back by the user. the contents of the external gain registers can also be read. to read the contents of any register, the user must fi rst write to the control register by writing 0001 to the wr3 to wr0 bits via the pd0/d in pin (see table 10 ). the next four bits in the control register are the rd bits, which are used to select the desired register from which to r ead. the appropriate 4- bit addresses for each of the offset and gain registers are listed in table 11 . the remaining eight sclk cycle bits are used to set the remaining bits in the control register to the desired state for the nex t adc conversion. the 19 th sclk falling edge clocks out the first data bit of the digital code corresponding to the value stored in the selected internal device register on the d out a pin. d out b outputs the conversion result from adc b. when the selected r egister has been read, the control register must be reset to output the adc results for future conversions. this is achieved by writing 0001 to the wr3 to wr0 bits, followed by 0000 to the rd bits. the remaining eight bits in the control register should th en be set to the required configuration for the next adc conversion. 06732-031 cs sclk d out a pd0/d in 10 14 16 three-s ta te 11 12 13 17 three- s ta te 15 db12 a db13 a 18 20 19 32 33 db0 a three-s ta te rd1 rd0 msb db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 rd2 rd3 t 2 t 8 t quiet 9 8 7 65432 1 t 13 t 14 figure 31 . timing diagram for writing to a register 06732-032 cs sclk d out a pd0/d in 10 14 16 three-s ta te 11 12 13 17 three- s ta te 15 db12 a db13 a 18 20 19 32 33 db0 a three-s ta te 0 1 rd3 rd2 rd1 rd0 0 0 0 0 0 0 0 0 00 t 2 t 13 t 14 t 8 t quiet 9 8 7 65432 1 figure 32 . timing diagram for a read operation with pd0/d in as an input data sheet AD7264 rev. b | page 23 of 28 seri al interface figure 33 and figure 34 show the detailed timing diagrams for the serial interface on the AD7264. the serial clock provides the conversion clock and controls the transfer of information from the AD7264 after the conversion. the AD7264 ha s two output pins corresponding to each adc. data can be read from the AD7264 using both d out a and d out b. alternatively, a single output pin of the users choice can be used. the sclk input signal provides the clock source for the serial interface. the falling edge of cs puts the track - and - hold into hold mode, at which point the analog input is sampled. the conversion is also initiated at this point and requires a minimum of 19 sclk cycles to complete. the d out x lines remain in three - state while the conversion is taking place. on t he 19 th sclk falling edge, the AD7264 returns to track mode and the d out a and d out b lines are enabled. the data stream co nsists of 14 bits of data, msb first. the m sb of the conversion result is clocked out on the 19 th sclk falling edge to be read by the microcontroller or dsp on the subsequent sclk falling edge (the 20 th falling edge). the remaining data is then clocked out by subsequent sclk falling edges. thus, th e 20 th falling clock edge on the serial clock has the msb provided and also clocks out the second data bit. the remainder of the 14 - bit result follows, with the final bit in the data transfer being valid for reading on the 33 rd falling edge. the lsb is pro vided on the 32 nd falling clock edge. the AD7264 -5, with its 20 mhz sclk frequency , easily facilitates reading on the sclk falling edge. when using a v drive voltage of 5 v with the AD7264 , the maximum specified access time (t 4 ) is 23 ns, which enables rea ding on the subse - quent falling sclk edge after the data has been clocked out, as described previously. however, if a v drive voltage of 3 v is used for the AD7264 and the setup time of the microcontroller or dsp is too large to enable reading on the falling sclk edge, it may be necessary to read on the sclk rising edge. in this case, the msb of the co nversion result is clocked out on the 19 th sclk falling edge to be read on the 20 th sclk rising edge, as shown in figure 35 . this is possible because the hold time (t 5 ) is longer for lower v drive voltages. if the data acce ss time is too long to accom - modate the setup time of the chosen processor , an alternative to reading on the rising sclk edge is to use a slower sclk frequency. on th e rising edge of cs , d out a and d out b go back into three - state. if cs is not brought high after 33 sclk cycles but is instead held low for an additional 14 sclk cycles, the data from adc b is output on d out a after the adc a result. likewise, the data from adc a is output on d out b after the adc b result. this is illustrated in figure 34 , which shows the d out a example. in this case, the d out line in use goes back into three - state on the 47 th sclk fa lling edge or the rising edge of cs , whichever occurs first. if the falling edge of sclk coincides with the falling edge of cs , the falling edge of sclk is not acknowledged by the AD7264, and the next falling edge of sclk is the first one registered after the falling edge of cs . cs sclk 1 5 19 d out a three-s ta te t 4 2 3 4 20 t 5 three- state t 7 t 3 18 db 11 a db12 a db13 a 21 31 32 33 db1 a db0 a d out b three-s ta te three- state db 11 b db12 b db13 b db1 b db0 b 06732-033 t 2 t 9 t 8 t quiet t 6 first data bit clocked out on this edge first data bit read on this edge figure 33 . normal mode operation 06732-034 cs 32 33 31 21 20 19 18 d out a three-s ta te three- state sclk 1 2 45 46 47 db13 a db12 a db1 a db0 a db13 b db12 b db1 b db0 b t 10 figure 34 . reading data from both adcs on one d out line with 47 sclk cycles AD7264 data sheet rev. b | page 24 of 28 cs sclk 1 5 19 d out a three-s ta te t 4 2 3 4 20 t 5 three- sta te 18 db 11 a db12 a db13 a 21 22 31 32 33 db1 a db0 a d out b three-s ta te three- sta te db 11 b db12 b db13 b db1 b db0 b 06732-039 t 2 t 8 first data bit clocked out on this edge first data bit read on this edge figure 35 . serial interface timing diagram when reading data on the rising sclk edge with v drive = 3 v data sheet AD7264 rev. b | page 25 of 28 calibration internal offset cali bration the AD7264 allows the user to calibrate the offset of the device using the cal pin. this is achi eved by setting the cal pin to a high logic level, which initiates a calibration on the next cs falling edge. the calibration requires one full conversion cycle, which contains a cs falling edge followed by 19 sclk cycle s. the cal pin can remain high for more than one conversion , if desired , and the AD7264 continues to calibrate. the cal pin should be driven high only when the cs pin is high or after 19 sclk cycles have elapsed when cs is low, that is, between conversions. the cal pin must be driven high t 12 before cs goes low. if the cs pin goes low before t 12 elapses, the calibration result will be inaccurate f or the current conversion ; if the cal pin remains high, the subsequent calibration conver - sion is correct. if the cal pin is set to a logic high state during a conversion, that conversion result is corrupted. if the cal pin has been held high for a minimum of one conversion and when t 12 and t 11 have been adhered to, the calibration is complete after the 19 th sclk cycle and the cal pin can be driven to a logic low state. the next cs falling edge after the cal pin has been driven to a low logic state initiates a conversion of t he differential analog input signal for both adc a and adc b. alternatively , the control register can be used to initiate an offset calibration. this is done by setting the cal bit in the control register to 1. the calibration is then initiated on the nex t cs falling edge, but the current conversion is corrupted. the adcs on the AD7264 must remain fully powered up to complete the internal calibration. the AD7264 registers store the offset value, which can easily be accessed by the user (see the reading from a register section). when the device is calibrating, the differential analog inputs for each respective adc are shorted together internally and a conversion is performed. a digital code representing the offs et is stored internally in the offset registers, and subsequent conver - sion results have this measured offset removed. when the AD7264 is calibrated, the calibration results stored in the internal device registers are relevant only for the particular pga gain selected at the time of calibration. if the pga gain is changed, the AD7264 must be recalibrated. if the device is not recalibrated when the pga gain is changed, the offset for the previous gain setting continues to be removed from the digital output code, which may lead to inaccuracies. the offset range that can be calibrated for is 500 lsb at a gain of 1. the maximum offset voltage that can be calibrated for is reduced as the gain of the pga is increased. ta ble 12 details the ma ximum offset voltage that can be removed by the AD7264 without compromising the available digital output code range. the least significant bit size is av cc /2 b it s , which is 5/16,384 or 305 v for the AD7264 . the maximum removable offse t voltage is given by gain v 305 lsb500 table 12 . offset voltage range gain maximum removable offset voltage 1 152.5 mv 2 76.25 mv 3 50.83 mv 32 4.765 mv 06732-035 cs sclk ca l 20 1 2 3 21 19 t 2 t 6 t 8 t 7 t 12 t 11 33 32 21 20 19 321 figure 36 . calibration timing di agram AD7264 data sheet rev. b | page 26 of 28 adjusting the offset calibration register the internal offset calibration register can be adjusted manually to compensate for any signal path offset from the sensors to the adc. no internal calibration is required , and the cal pin can remain at a l ow logic state. by changing the contents of the offset register, different amounts of offset on the analog input signal can be compensated for. use the following steps to determine the digital code to be written to the offset register: 1. configure the sensor to its offset state. 2. perform a number of conversions using the AD7264. 3. take the mean digital output code from both d out a and d out b. this is a 14 - bit result but the offset register is only 12 bits ; thus , the 14 - bit result needs to be converted to a 12- bit result that can be stored in the offset register. this is achieved by keeping the sign bit and removing the second and third msbs. 4. the resultant digital code can then be written to the offset registers to calibrate the AD7264. example: mean digital code from d out a = 8100 (01 1111 1010 0100) code written to offset register = 0111 1010 0100 if a +10 mv offset is present in the analog input signal and the gain of the pga is 2, the code that needs to be wri tten to the offset register to compensate for the offset is )2 v/ 305( mv10 + = 65.57 = 0000 0100 0001 if a ?10 mv offset is present in the analog input signal and the gain of the pga is 2, the code that needs to be written to the offset register to compensate for the offset is )2 v/ 305( mv10 ? = ?65.57 = 1000 0100 0001 system gain calibrat ion the AD7264 also allow s the user to write to an external gain register, thus enabling the removal of any overall system gain error. both adc a and adc b have independent external gain registers, allowing the user to calibrate independently the gain on both adc a and adc b signal paths. the gain calibration feature can be used to implement accurate gain matching between adc a and adc b. the system calibration function is used by setting the sensors to which the AD7264 is connected to a 0 gain state. the AD7264 converts this analog input to a digital output code, which corres ponds to the system gain and is available on the d out pins, this digital output code c an then be stored in the appropriate external register. for details on how to write to a register, see the writing to a register section and table 11 . the gain calibration register contains seven bits of data. by changing the contents of the gain register, different amounts of gain on the analog input signal can be compensated for. the msb is a sign bit, while the remaining six bits store the m ultiplica tion factor, which is used to adjust the analog input range. the gain register value is effectively multiplied by the analog input to scale the conversion result over the full range. increasing the gain register multiplication factor compensates for a larger analog input range, and decreasing the gain registe r multiplier compensates for a smaller analog input range. each bit in the gain calibration register has a resolution of 2.4 10 ?4 v (1/4096). a maximum of 1.538% of the analog range can be calibrated for. the multiplier factor stored in the gain register can be decoded as outlined in table 13. the gain registers can be cleared by writing all 0s to each re gister , as described in the writing to a register section. for accurate gain calibration, both the positive and negative full - scale digital output codes should be measured prior to determining the multiplication factor that is written to the gain register. table 13 . decoding of multiplication factors for gain calibration analog input (v) digital gain error (lsb) gain register code (sign b it + 6 b its) multiplier equation (1 x /4096) multiplier value comments v in max 0 lsb 0 000000 1 ? 0/4096 1 sign bit = 0; negative sign in multiplier equation v in max ? 244 v ?2 lsb 0 000001 1 ? 1/4096 0.999755859 sign bit = 0 ; negative sign in multiplier equation v in max ? (63 244 v) ?126 lsb 0 111111 1 ? 63/4 096 0.98461914 sign bit = 0 ; negative sign in multiplier equation v in max 0 lsb 1 000000 1 + 0/4096 1 sign bit = 1 ; plus sign in multiplier equation v in max + 244 v +2 lsb 1 000001 1 + 1/4096 1.000244141 sign bit = 1 ; plus sign in multiplier equation v in max + (63 244 v) +126 lsb 1 111111 1 + 63/4096 1.015380859 sign bit = 1 ; plus sign in multip lier equation data sheet AD7264 rev. b | page 27 of 28 application hints grounding and layout the analog and digital supplies to the AD7264 are independent and separately pinned out to minimize co upling between the analog and digital sections of the device. the printed circuit board (pcb) that houses the AD7264 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. this design facilitate s the use of ground planes that can be easily separated. to provide optimum shielding for ground planes, a minimum etch technique is generally best. all five agnd pins of the AD7264 should be sunk in the agnd plane. digital and analog ground planes should be joined in only one place. if the AD7264 is in a system where multiple devices require an agnd to dgnd connection, the connection should still be made at only one point , a star ground point , that should be established as close as possible to the ground pins on the AD7264. avoid running digital lines under the device because this couples noise onto the die. however, the analog ground plane should be allowed to run under the AD7264 to avoid noise coupling. the power supply lines to the AD7264 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the p ower supply line. to avoid radiating noise to other sections of the board, fast switching signals, such as clocks, should be shielded with digital ground , and clock signals should never run near the analog inputs . avoid crossover of digital and analog signals. to reduce the effects of feedthrough within the board, traces on opposite sides of the board should run at right angles to each other. a microstrip technique is the best method but is not always possible with a double - sided board. in this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. good decoupling is also important. all analog supplies should be decoupled with 10 f tantalum capacitors in parallel with 100 nf capacitors to gnd. to achieve the best results from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. the 0.1 f capacitors should have low effective series resistance (esr) and low effective series inductance (esi), such as the common ceramic types or surface - mount types. these low esr and low esi capacitors provide a low impedance path to ground at h igh frequencies to handle transient currents due to internal logic switching. pcb design guideline s for lfcsp the lands on the chip scale package (cp - 48- 1) are rectangular. the pcb pad for these should be 0.1 mm longer than the package land length, and 0 .05 mm wider than the package land width, leaving a portion of the pad exposed. to ensure that the solder joint size is maximized, the land should be centered on the pad. the bottom of the chip scale package has a thermal pad. the thermal pad on the pcb s hould be at least as large as the exposed pad. on the pcb, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern to ensure that shorting is avoided. t o improve thermal performance of the package, us e thermal vias on the pcb, incorporating them in the thermal pad at 1.2 mm pitch grid. the via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz copper to plug the via. the user should connect the pcb thermal pad to agnd. AD7264 data sheet rev. b | page 28 of 28 outline dimensions compliant to jedec standards mo-220-vkkd-2 1 48 12 13 37 36 24 25 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.80 max 0.65 typ 5.50 ref coplanarity 0.08 0.20 ref 1.00 0.85 0.80 0.05 max 0.02 nom sea ting plane 12 max top view 0.60 max 0.60 max pin 1 indic at or 0.50 ref pin 1 indic at or 0.25 min 7.10 7.00 sq 6.90 6.85 6.75 sq 6.65 06-05-2012- a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. exposed p ad figure 37 . 48 - lead lead frame chip scale package [lfcsp_vq] 7 mm 7 mm body, very thin quad (cp - 48 -1) dimensions shown in millimeters compliant t o jedec s t andards ms-026-bbc top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc lead pitch 1.60 max 0.75 0.60 0.45 view a pin 1 0.20 0.09 1.45 1.40 1.35 0.08 coplanarit y view a ro ta ted 90 ccw se a ting plane 7 3.5 0 0.15 0.05 9.20 9.00 sq 8.80 7.20 7.00 sq 6.80 051706- a figure 38 . 48 - lead low profile qu ad flat package [lqfp] (st - 48) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD7264bcpz ? 40c to +105c 48 - lead lead frame chip scale package [lfcsp_vq] cp - 48 - 1 AD7264bcpz -rl7 ? 40c to +105c 48- lead lead frame chip scale package [lfcsp_vq] cp -48 -1 AD7264bcpz - 5 ? 40c to +105c 48 - lead lead frame chip scale package [lfcsp_vq] cp - 48 - 1 AD7264 bcpz - 5 - rl7 ? 40c to +105c 48 - lead lead frame chip scale package [lfcsp_vq] cp - 48 - 1 AD7264bstz ? 40c to +105c 48 - lead low profile quad flat package [lqfp] st - 48 AD7264bstz - rl7 ? 40c to +105c 48 - lead low profile quad flat package [lqfp] st - 48 AD7264bst z - 5 ? 40c to +105c 48 - lead low profile quad flat package [lqfp] st - 48 AD7264bstz -5- rl7 ? 40c to +105c 48- lead low profile quad flat package [lqfp] st- 48 eval - AD7264edz evaluation board eval - ced1z development board 1 z = rohs compliant part. ? 2008 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06732 -0- 11 / 12(b) |
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